Acrosser Technology Co. Ltd, a global professional industrial and embedded computer provider, announces the new Mini-ITX mainboard, AMB-D255T3, which carries the Intel dual- core 1.86GHz Atom Processor D2550. AMB-D255T3 features onboard graphics via VGA and HDMI, DDR3 SO-DIMM support, PCI slot, mSATA socket with SATA & USB signals, and ATX connector for easy power in. AMB-D255T3 also provides complete I/O such as 6 x COM ports, 6 x USB2.0 ports, 2 x GbE RJ-45 ports, and 2 x SATA port. AMB-D255T3 can support dual displays via VGA, HDMI or 18-bit LVDS. AMB-D255T3 has one MiniPCIe type slot and one PCI for customer’s expansion. The MiniPCIe slot works with SATA and USB signals that can be equipped with mSATA storage module. for
more information, please visit: http://www.acrosser.com/News-Newsletter/62.html
AR-V6100FL features fanless operation with Intel Core i7-2710QE 45W CPU. Its excellent thermal design makes it a popular industry choice for In-Vehicle PCs. The efficiency of heat dissipation also contributes to its high performance under rugged automotive environments. Another fascinating feature of AR-V6100FL is its smart power management function. Acrosser built a comprehensive power management subsystem solution, allowing users to select the best setting for the power management mode to meet specific application demands.
To reduce the amount of R&D work, lower costs and shorten their products’ time to market, they seek ways to cut down their initial development and migration tasks. One approach is to make use of a hardware vendor’ migration services. AMD Embedded G-Series platform are their discrete-level graphics embedded computer capabilities. Providing support for the latest DirectXR 11 API, they enhance all conventional graphics-intensive small-form-factor embedded computer applications. OEMs also face the challenge of implementing this state-of-the-art technology in their new or existing applications, including validation and verification of the applications’ functionality and access to hardware functions and I/Os.
Most engineers and system integrators find it troublesome when installing car computers in their business vehicle. How often did hardware configuration or software programming take away from their business? Above all these worries, establishing steady power management becomes the most important issue before integrating the entire system. Acrosser’s In-Vehicle computer offers 6 stunning power management traits to overcome these difficulties.
Feature 1: Wide Range Power Input
Vehicles usually take 2 types of battery voltage: 12V or 24V. However, Acrosser’s power manage subsystem has a wide range for power inputs that cater to both batteries. This could also protect the system from unstable power surges during the vehicle’s operation.
Feature 2: Battery Monitoring
Large energy consumption may occur while operating the car computer. To prevent the power loss, Acrosser’s In-Vehicle computer offers low voltage protection to monitor the main battery. Once the voltage goes below its pre-set value, the computer will shut down and save the energy for vehicle use.
Feature 3: Power On/Off Retry
When the In-vehicle computer power on/off mode is controlled by the car ignition, it is impossible to turn off the ignition and turn it back on just to restart the computer. If the vehicle’s ignition switch did not power up the computer properly, Acrosser’s power management subsystem will automatically detect and monitor the system status to restart the system upon retry.
Feature 4: User-friendly Interface
Acrosser’s in-vehicle computer adopts user-friendly interface, allowing vehicle drivers to easily define its own power management according to their special needs. For instance, different industries may have little in common when setting its power delay time or on/off control mode. Resetting the default in-vehicle computer may take a long time, but that would not be the case if you are using a user-friendly interface.
Feature 5: Status LED
Most of the In-Vehicle computers are not equipped with displays, making them difficult for users to act when error occurs. Installed with status LED, Acrosser’s In-Vehicle computer precisely reflects its status quo to its user.
Feature 6: Power Delay Control
In case of zero power supply occurring after switching off the vehicle ignition, Acrosser’s “power delay control” function enables the In-vehicle computer can still operate for a short period after switching off. Therefore, the user may upload or synchronize data with control center and complete the task.
ACROSSER Technology has provided a complete product line for In-Vehicle computers. The product line also gained more attention after winning the 21th Taiwan Excellence Award with 2 outstanding In-Vehicle computers: AR-V6005FL and AR-V6100FL. Acrosser also released its latest in-vehicle computer, AIV-HM76V0FL during late 2012. The company pride itself in offering not just products, but solutions. Please contact ACROSSER Technology for further consultations, volume quotes, or any other questions.
With a total board height less than 20mm, the slim fit feature of AMB-D255T1 makes it a perfect applicationalmost everywhere. With single layer I/O ports and external +12V DC power input, AMB-D255T1 can easily be equipped even in limited spaces like digital signage, POS or thin client systems. Also, the supporting video source includes both VGA and HDMI outputs to cater to a variety of needs. Many digital signage partners have showed great interests toward AMB-D255T1 for their business sector. AMB-D255T1 has one DDR3 SO-DIMM which supports up to 4GB DDR3 memory, mSATA socket with USB signals and SIM slot, and a DC jack for easy power in. For customers that are taking their entire system to the next level, AMB-D255T1 provides one PCI slot and one Mini PCIe expansion slot with a SIM card socket for further improvement. The mini PCIe expansion allows mSATA to function together with the system or multi module choices for USB signals module installation.( mSATA storage, Wi-Fi module, or 3G/4G telecommunication)
The key features of the AMB-D255T1 include: ．Intel Atom D2550 1.86GHz ．1 x DDR3 SO-DIMM up to 4GB ．1 x VGA ．1 x HDMI ．1 x 24-bit LVDS ．6 x USB2.0 ．4 x COM ．1 x GbE (Realtek RTL8105E) ．1 x PS/2 KB/MS ．1 x PCI slot ．1 x MiniPCIe slot for mSATA and USB device ．1 x SATA with power connector ．8-bit GPIO
ACROSSER Technology, a world-leading In-Vehicle
Computer designer and manufacturer, is pleased to introduce its latest
In-Vehicle computer product, the AIV-HM76V0FL.
The AIV-HM76V0FL is built for handling rugged environments. To showcase its high
performance, we have created a small experiment to prove its durability in
difficult situations.
One fascinating feature of AIV-HM76V0FL is its ability to support HDMI video
output. This outstanding feature would satisfy those seeking for high-quality
video outputs. AIV-HM76V0FL is an outstanding In-Vehicle solution for anything
ranging from commercial to security issues. We have seen our clients using them
on digital signage display and security IP surveillance cameras. The two key
factors that allow for such high-performance graphic processing are the Intel
HM76 mobile chipset and FCPGA 988 socket for 3rd generation Core i
mobile computer platform.
Acrosser’s latest In-Vehicle computer product, AIV-HM76V0FL should meerit a
spot on your procurement list. This product can sustain a level 2G shock and
received IEC 60068-2-64 (anti-vibration) and IEC
60068-2-27 (anti-shock) certifications.
Here is the actual video demonstrating the outstanding performance of the
AIV-HM76V0FL. The base vibrator simulates a mobile environment, and this is
exactly how it looks like inside a moving vehicle.
AIV-HM76V0FL Features
‧ FCPGA 988 socket support Intel 3rd Generation Core
i7/i5/i3 and Celeron processors
up to 45W i7-3720QM
‧ Fanless thermal design and anti-vibration industrial design
‧ HDMI/DVI/VGA video outputs
‧ Combo connector for Acrosser’s In-Vehicle monitor
‧ 4 external USB 3.0 ports
‧ CAN bus 2.0 A/B
‧ Wi-Fi, Bluetooth, 3.5G, GPS
‧ One-wire (i-Button) interface
ACROSSER Technology, a world-leading In-Vehicle Computer designer and manufacturer, is pleased to introduce its latest In-Vehicle computer product, the AIV-HM76V0FL. The AIV-HM76V0FL is built for handling rugged environments. To showcase its high performance, we have created a small experiment to prove its durability in difficult situations.
One fascinating feature of AIV-HM76V0FL is its ability to support HDMI video output. This outstanding feature would satisfy those seeking for high-quality video outputs. AIV-HM76V0FL is an outstanding In-Vehicle solution for anything ranging from commercial to security issues. We have seen our clients using them on digital signage display and security IP surveillance cameras. The two key factors that allow for such high-performance graphic processing are the Intel HM76 mobile chipset and FCPGA 988 socket for 3rd generation Core i mobile computer platform.
Acrosser’s latest In-Vehicle computer product, AIV-HM76V0FL should meerit a spot on your procurement list. This product can sustain a level 2G shock and received IEC 60068-2-64 (anti-vibration) and IEC 60068-2-27 (anti-shock) certifications.
Here is the actual video demonstrating the outstanding performance of the AIV-HM76V0FL. The base vibrator simulates a mobile environment, and this is exactly how it looks like inside a moving vehicle.
AIV-HM76V0FL Features ‧ FCPGA 988 socket support Intel 3rd Generation
Core i7/i5/i3 and Celeron processors up to 45W
i7-3720QM ‧ Fanless thermal design and anti-vibration industrial design ‧
HDMI/DVI/VGA video outputs ‧ Combo connector for Acrosser’s In-Vehicle
monitor ‧ 4 external USB 3.0 ports ‧ CAN bus 2.0 A/B ‧ Wi-Fi,
Bluetooth, 3.5G, GPS ‧ One-wire (i-Button) interface
A portable atomic clock is just the ticket for many UAVs, and the more SWaP-optimized the better. The Chip-Scale Atomic Clock (CSAC) fits the bill with the low power draw and accurate performance inherent in its design.
Unmanned Aerial Vehicles (UAVs) began as tools for military surveillance. As their capabilities expanded, they found usage in civilian applications such as border patrols and drug interdiction, while on the military side the expanded capabilities led to missions using armed UAVs.Throughout their use, accurate clocks have been required for UAVs to carry out their missions. A principal need has been navigation; UAVs typically use a clock that has been synchronized to Global Positioning System (GPS) for very accurate timing. However, when the GPS signal is lost, the clock is used to provide a “holdover” function that integrates with a backup navigation system, usually some form of an Inertial Navigation System (INS). The clock’s holdover performance is important because, in military applications, GPS signal loss is sometimes due to intentional jamming, which can persist for long periods of time.Accurate clocks are also needed in UAV communications. As UAV sensor payloads have advanced from still photos to video, to video integrated with infrared and other sensor data, high-density encryptedwaveforms have been employed to transmit this data, as well as to receive vehicle control data. These waveforms can only stay synchronized with stable, accurate clocks. ............ refer to http://smallformfactors.com/articles/chip-scale-swap-design-challenges/#at_pco=cfd-1.0
ANR-IB751N1/A/Bnetworking appliances.
ANR-IB751N1/A/B networking appliances are the latest in scalable Intel
3rd generation Core i7/i5/i3 processors (formerly code-named Ivy
Bridge).
ANR-IB75N1/A/B is a rackmount platform (440x372x44mm) which can be
installed in the 19” rack. It can carry a 3rd generation Intel Core i
i3, i5, i7, or Pentium processors to deliver higher efficiency,
increased processing throughput, and improved performance on
applications. ANR-IB75N1/A/B also comes equipped with a maximum 16GB
DDR3 memory and optional 2 or 4 x SFP and 8 x LAN ports. System
Integrators can select different configurations for their network
appliances. It offers the best P/P ratio in applications like the UTM,
IDS/IPS, VPN, Firewall, Anti-Virus, Anti-Spam, RSA gateway, QoS,
streaming.
Virtualization trends in commercial computing offer benefits for cost, reliability, and security, but pose a challenge for military operators who need to visualize lossless imagery in real time. 10 GbE technology enables a standard zero client solution for viewing pixel-perfect C4ISR sensor and graphics information with near zero interactive latency.
For C4ISR systems, ready access to and sharing of visual information at any operator position can increase situational awareness and mission effectiveness. Operators utilize multiple information sources including computers and camera feeds, as well as high-fidelity radar and sonar imagery. Deterministic real-time interaction with remote computers and sensors is required to shorten decision loops and enable rapid actions.A zero client represents the smallest hardware footprint available for manned positions in a distributed computing environment. Zero clients provide user access to remote computers through a networked remote desktop connection or virtual desktop infrastructure. Utilizing a 10 GbE media network for interconnecting multiple computers, sensors, and clients provides the real-time performance and image quality required for critical visualization operations. The cost of deploying a 10 GbE infrastructure is falling rapidly and 10G/40G has become the baseline for data center server interconnect. Additionally, deploying common multifunction crew-station equipment at all operator positions brings system-level cost and logistics benefits. The following discussion examines the evolution to thinner clients and the path to a real-time service-oriented architecture, in addition to looking at zero client benefits and applications.
1.Evolution to thinner clients 2.Path to a real-time service-oriented architecture 3.Zero client benefits 4.Reduced total cost of ownership 5.Reduced size, weight, and power 6.High system availability 7.High system security 8.System agility 9.Applications of a zero client 10.Mission-critical solution
the new Atom series solutions which include AMB-D255T1Mini-ITX industrial mainboard and AMB-N280S1 fanless 3.5-inch single board computer. AMB-D255T1 is equipped with an Intel D2550 Atom processor. AMB-N280S1 is equipped with an Intel N2800 Atom. Both have a 5~7 year product warranty.
Acrosser is providing a special price for these two boards to make them available for customers sooner. Please contact your local sales for more information.
This seems to be the year for milestone events in the EDA industry,
though calculations show some of the “anniversary” designations to be
premature. Nevertheless, the first big EDA event of the year is the
Design and Verification Conference (DVCon),
held in San Jose, CA every February. DVCon celebrated its 10th
anniversary this year, after a transformation from HDLcon in 2003, which
followed the earlier union of theVHDLInternational User’s Forum and InternationalVerilogHDL Conference. Those predecessor conferences trace their origins back 25 years and 20 years, respectively.
After DVCon, EDA marketers quickly turn to preparations for the JuneDesign Automation Conference(DAC), perhaps with a warm-up at Design, Automation, andTestin
Europe (DATE) in March. DAC is the big show, however, and this year
marks the 50th such event (and its 49th anniversary). Phil Kaufman Award
winner Pat Pistilli received the EDA industry’s’ highest honor for his
pioneer work in creating DAC, which grew from his amusingly-named
Society to Help Avoid Redundant Effort (SHARE) conference in 1964.
Milestones
inevitably lead to some reflection, but also provide an opportunity to
look forward to what the future will bring. In our 2nd annual EDA Digest
Resource Guide, we will be asking EDA companies to share what they see
as the biggest challenges facing the industry in the next five years,
and how the industry will change to meet those challenges. Will future
innovations be able to match the impact of the greatest past
developments in EDA, which enabled the advances in electronics that we
benefit from today?
To
put that question in perspective, I’ve been developing a Top 10 list of
the most significant developments in the history of EDA, based on my
personal experiences over the course of my career. That doesn’t go back
quite as far as Pat Pistilli’s, but I have seen many of the major
developments in EDA first hand, going back to when I started as an IC
designer at Texas Instruments. (This was a few years after we stopped
cutting rubylith, in case you were wondering.)
We will also be conducting asurveyof
readers, and will publish the results in the EDA Digest Resource guide
in time for DAC-50. To get things started, here are the first five EDA
breakthroughs on my list, roughly in historical order.
CALMA GRAPHIC DATA STATION
The first of my Top-10 developments in EDA is the Calma Graphic Data Station, or GDS. To this day the semiconductor industry still utilizes the GDS-II data format developed by Calma as the standard for IC design “tapeouts.” When I started at TI, draftsmen created chip layouts manually with pencil and gridded paper. Those drawings then had to be digitized, which amounted to clicking with a pointingdeviceon every vertex of the layout, to create an electronic database of the IC geometries. This would later be converted by software to a pattern generator format for fabricating the photomasks.
Evolving from the editing of digitized drawings to creating the IC layers in CAD from the beginning, Calma led the way in replacing the error-prone manual drafting process with a dedicated computer and software that automated the process. Calma spawned the EDA era for layout design of both ICs and printed circuit boards, which led to the adoption of Apollo and Sun Microsystems workstations, and the creation of companies such as Mentor Graphics.
SPICE
There should be no argument that the Simulation Program with Integrated Circuit Emphasis, or SPICE, is the most ubiquitous and long-lived tool in the history of the EDA industry. Like Calma, SPICE preceded the industry itself. The 40th anniversary of the creation of SPICE at UC Berkeley was celebrated at the Computer History Museum in 2011. Even if you work as a system-level designer, and your view of the chip design is in C++ or some other higher-level language, your end result still relies on a commercial offspring of SPICE for modeling the semiconductor process and developing the logic libraries for synthesis. If you are a PCB designer, you’ve probably used PSPICE tomodelyour circuits before fabrication.
THE LEVEL 28 TRANSISTOR MODEL, AND HSPICE
I expect that many will be surprised by this choice, but it is based on my first-hand experience. When I was at TI they had their own CAD group that created TI-SPICE. The same was true of other Integrated Device Manufacturers (IDMs) such as Motorola,AnalogDevices, and IBM. When I moved on to the GE Research Lab to form a new VLSI design group, we quickly found that Berkeley SPICE was great as a learning tool, but it wasn’t close to industrial strength in accuracy or robustness, frequently resulting in the dreaded “Failure to Converge” message. Public SPICE transistormodelswere also too primitive for the advanced process we were developing. Meta-Software solved the first problem with HSPICE, but their lesser-known secret sauce was their device modeling lab. With Meta-Software’s process modeling kits for foundries, Level 28 became the de facto industry standard, years before the Berkeley Short-channel IGFET Model (BSIM). Meta-Software deserves credit for enabling the development of the fabless semiconductor industry. Eventually, the industry chose to not be locked into a proprietary model, but Level 28 served as the benchmark that drove BSIM-3 and other public-domain models to industrial quality.
HARDWARE DESCRIPTION LANGUAGES: VERILOG AND VHDL
What SPICE is to transistor-level design, the Verilog and VHDL Hardware Description Languages (HDLs) and their associated simulators became to logic design. Just as there were predecessors to SPICE, there were also logic simulators before GatewayDesign Automation created Verilog-XL. VHDL had its origin in the U.S. Department of Defense, and the ‘V’ in its name stands for the DoD’s Very High-Speed Integrated Circuit (VHSIC) program. Verilog and VHDL were often considered competing HDLs, but in 2000 their respective standards organizations, VHDL International (VI) and Open Verilog International (OVI), were merged to form Accellera.
DESIGN COMPILER
UntilSynopsys’ Design Compiler created the ability to perform logic synthesis, all IC design was at the transistor level. Design Compiler hid that detail from digital designers by automating the mapping of HDL to pre-constructed libraries of logic cells. Though competitors later came on the scene, the automation of ASIC designs began with Design Compiler. Synopsys, too, recently celebrated a milestone with their 25th anniversary in 2011.
ROUNDING OUT THE LIST
With nearly 50 DACs to showcase developments in the EDA industry, there are a lot to choose from when coming up with a Top 10 list. I believe few, however, have had the impact of the five developments that start out my list. As DVCon shows, design complexity has shifted much of the industry’s focus to verification. Are new developments keeping up with the challenge? I can think of several newer innovations to round out my list.What EDA developments would be on your Top 10 list?
As you ponder that question, here’s a puzzler that may require a bit of detective work: What do Calma, Synopsys and Meta-Software have in common?
Be assured, though, that the answers are out there on the Internet. Send me your answers if you think you know.
Also, be sure to take oursurveyto contribute to the Top 10 and be entered to win a $100 Visa gift card.
MicroMax announced today it is exhibiting its M-Max 810 PR/MS3, an ATR-based system for avionics, at Embedded World 2013 in Nuremberg.
Sam Abarbanel, President of MicroMax, stated “Our newest addition to the M-Max line of rugged computers demonstrates MicroMax’s excellence at building tough machines for harsh environments. Our unique fully sealed fanless ATRenclosure is especially designed to house PC/104 form-factor boards. We proudly demonstrate this system at Embedded World as yet another example of our quality engineering and manufacturing abilities.”
The M-Max 810 PR/MS3 high-performance rugged industrial computer provides reliable operation in tough environments including transportation (ground, rail, air and marine), mining and processing applications. The fully-ruggedized ATR-type aluminum chassis is fanless and uses natural convection and conduction cooling in accordance with MIL-STD-810 standards. COTS technology components allow configuring the M-Max 810 family to comply with a wide variety of airborne, marine and ground vehicle applications. Providing shock and vibration protection, the Max 810 PR/MS3 can operate under extreme temperatures, dust and humidity. Delivering excellent performance comparable to high-end desktop systems, it also features excellent 2D and 3D graphics capabilities as well as hardware video decoding.
To support using high performance processors when passive cooling and a small enclosure are mandatory, MicroMax developed technology to dissipate excessive heat from computer boards and other electronic devices working in high vibration environments. This patented design efficiently removes heat from electronic components housed on a circuit board vibroinsulated from an enclosure.
MicroMax, as a manufacturer of industrial computers, takes a customized approach to each client. Our engineering group can design M-Max systems to fit customer-specific technical requirements.
Software
architects designing critical embedded systems have tough choices to make when
selecting an operating system. Decisions can be both simplified and complicated
with new framework and platform initiatives coming into being.
Operating
systems that control critical embedded systems have many stringent
requirements that they must be able to address in order for them to be
considered for deployment. There will always be debate about the best operating
systems to deploy in critical applications. However, improvements in real-time
operating capabilities in Windows and Linux have
opened up the door to options in addition to traditional Real-Time Operating Systems
(RTOSs).
Requirements to deploy
Most of the requirements to deploy a critical system are
based on the real-time response of the system to the processes they monitor and
control. The top requirements are related to:
Memory protection - A misbehaved thread can corrupt the
kernel's own code or internal data structures causing all types of bad behaviors
to the system.
Fault tolerance and high availability - Even the best
software has latent bugs. As applications become more complex and perform more
functions, the number of bugs in fielded systems continues to rise. System
designers must, therefore, plan for failures and employ fault recovery
techniques.
Mandatory vs. discretionary access control - Mandatory
access control provides guarantees to the access of a device or file. Discretionary access
controls are only as effective as the applications using them, and these
applications must be assumed to have bugs in them.
Guaranteed resource availability: space domain and time domain
- A critical process cannot, as a result of malicious or careless
execution of another process, run out of memory resources or deadlock due to
priority conflicts that block resources.
Schedulability - Meeting hard deadlines is especially
important, and missing a deadline can be a critical fault; the access to system
services must be deterministic.
Interrupt latency - Some interrupts are higher priority
and require a faster response time than others; how long it takes
to respond is critical.
Bounded execution times - Just as response time is
critical, how long a task takes to execute is also important.
Priority inversion - A lower task can block a higher
priority task; predictably resolving the block is a must.
Security - Everything is
becoming connected, so trusted computing is more important than ever to prevent
malicious attacks.
In response to growing pressure to boost the performance and trim down the size of embedded applications,standards
organizations meet regularly to optimize their portfolios in light of
the latest available technology. These updated standards take advantage
of new silicon architecture combining multiple processors, graphics
elements, and complex I/O to deliver the next generation of
preengineered, off-the-shelf modules to support many of the
high-performance requirements of embedded product development.
These
standardized computer platforms allow designers to trade in substantial
savings in Non-Recurring Engineering (NRE) and scheduling for slightly
higher recurring costs. Standards-based designs also shortcut the
software development effort by providing access to compatibleoperating systems, vendor-supplieddrivers, and sample firmware.
In
the Strategies section of this issue, we asked experts from several
standards organizations to bring us up to date on the latest changes
affectingembedded designs.
Starting things off, Jim Blazer, CTO at RTD Embedded Technologies and
active member of the PC/104 Consortium, presents the history and updates
in work – such as the latest generation of PCI Express – that support
the PC/104 stackable architecture. Citing the need for smaller and more
rugged building blocks, Alexander Lockinger, President of the Small Form
Factor Special Interest Group (SFF-SIG) and CTO at Ascend Electronics,
covers the trends and new products to expect in 2013. In addition,
Jerry Gipper, Director of Marketing atVITAandEditorial DirectorofVITA Technologiesmagazine,
reports on the recent Embedded Tech Trends 2013 meeting aboard the
Queen Mary and standards work in progress, plus some new technologies
such as optical interconnects.
We have expanded the Strategies section this month to bring you technical updates on a couple of developing trends in the intelligent systems marketplace. First, Andrew Patterson, Business Development Director for the Mentor GraphicsEmbedded SoftwareDivision, shows how open source opera-ting systems such asLinuxandAndroidare driving innovation in the in-vehicleinfotainment market. Next, Wil Florentino,Industrial AutomationMarketing Manager at Renesas Electronics, discusses the latest concepts available to integrate multipleanalogsensors into intelligent embedded devices. He explains how a configurable Analog Front End (AFE) simplifies the interface between these sensors and the digital world.
Regardless of the market segment, the software programming and certification phase has become the long pole in the embedded development tent. In this month’s Software section, we show how software design teams are adding advanced static code/analysis tools to the mix to shorten this extended development cycle and minimize post-release changes. Explaining the benefits and techniques used in static code analysis, Arthur Hicken, Wayne Ariola, and Adam Trujillo of Parasoftpresent several different analysis implementations and where they should be employed in the development process. Focusing on a single programming language, Jon Jarboe, Senior Technical Manager at Coverity, shows howstatic analysiscan be used to manage risk in aJava development environment. In addition, static analysis and contract-based programming can be combined to deliver softwarecomponentswith enhancedsafety and security, writes S. Tucker Taft, Vice President and Director of Language Research at AdaCore.
With requirements often changing over the course of a combined analog and digital development project, designers are turning to reconfigurable hardware to minimize schedule delays. In this issue’s Silicon section, Cypress Semiconductor Application Engineer Robert Murphy presents several examples showing how configurableSystem-on-Chip(SoC) peripherals can be combined to create multiple functional components. Speaking of reconfiguration, if you have ideas for future technical articles and coverage that would help in your design efforts, please let us know. Contributed articles are a great way to expose your technology or expertise to the embedded community, so if you have an idea, please send along an email with a short abstract.
802.11 networks are becoming nearly ubiquitous in many enterprise settings and can often be tapped to solve embedded
problems in the same location. In this example, a logistics cart used
for warehouse operations becomes 802.11 enabled, improving the
efficiency of a critical process.
In a tough economy with increased competition from global markets, companies are forced to do more with less. Supply chainmanagement
is one area where companies realize this challenge. Organizations are
continually struggling to ship more orders, decrease processing time,
and increase order accuracy, all the while reducing costs. The nature of
order processing has changed as well. With just-in-time and lean
manufacturing techniques becoming common practices, distribution
warehouses often need to process a high volume of small orders, which
often involve a large mix of products, adding further complexity to the
process.
IT managers are under increasing pressure to boost network capacity and performance to cope with the data deluge. Networking systems are under a similar form of stress with their performance degrading as new capabilities are added in software. The solution to both needs is next-generation System-on-Chip (SoC) communications processors that combine multiple cores with multiple hardware acceleration engines.
The data deluge, with its massive growth in both mobile and enterprise network traffic, is driving substantial changes in the architectures of base stations, routers, gateways, and other networking systems. To maintainhigh performanceas traffic volume and velocity continue to grow, next-generation communications processors combinemulticoreprocessors with specialized hardware acceleration engines inSoCICs.
The following discussion examines the role of the SoC in today’s network infrastructures, as well as how the SoC will evolve in coming years. Before doing so, it is instructive to consider some of the trends driving this need.
Networks under increasing stress
In mobile networks, per-user access bandwidth is increasing by more than an order of magnitude from 200-300 Mbps in 3G networks to 3-5 Gbps in 4G Long-Term Evolution (LTE) networks. Advanced LTE technology will double bandwidth again to 5-10 Gbps. Higher-speed access networks will need more and smaller cells to deliver these data rates reliably to a growing number of mobile devices.
In response to these and other trends, mobile base station features are changing significantly. Multipleradiosare being used incloudlike distributedantennasystems. Network topologies are flattening. Operators are offering advanced Quality of Service (QoS) and location-based services and moving to application-aware billing. The increased volume of traffic will begin to place considerable stress on both the access and backhaul portions of the network.
Traffic is similarly exploding withindata centernetworks. Organizations are pursuing limitless-scale computing workloads onvirtualmachines, which is breaking many of the traditional networking protocols and procedures. The network itself is also becoming virtual and shifting to a Network-as-a-Service (NaaS) paradigm, which is driving organizations to a more flexible Software-Defined Networking (SDN) architecture.
These trends will transform the data center into a private cloud with a service-oriented network. This private cloud will need to interact more seamlessly and securely with public cloud offerings in hybrid arrangements. The result will be the need for greater intelligence, scalability, and flexibility throughout the network.
Moore’s Law not keeping pace
Once upon a time, Moore’s Law – the doubling of processor performance every 18 months or so – was sufficient to keep pace with computing and networking requirements. Hardware and software advanced in lockstep in both computers and networking equipment. As software added more features with greater sophistication, advances in processors maintained satisfactory levels of performance. But then along came the data deluge.
In mobile networks, for example, traffic volume is growing by some 78 percent per year, owing mostly to the increase in video traffic. This is already causing considerable congestion, and the problem will only get worse when an estimated 50 billion mobile devices are in use by 2016 and the total volume of traffic grows by a factor of 50 in the coming decade.
In data centers, data volume and velocity are also growing exponentially. According to IDC, digital data creation is rising 60 percent per year. The research firm’s Digital Universe Study predicts that annual data creation will grow 44-fold between 2009 and 2020 to 35 zettabytes (35 trillion gigabytes). All of this data must be moved, stored, and analyzed, making Big Data a big problem for most organizations today.
With the data deluge demanding more from network infrastructures, vendors have applied a Band-Aid to the problem by adding new software-based features and functions in networking equipment. Software has now grown so complex that hardware has fallen behind. One way for hardware to catch up is to use processors with multiple cores. If one general-purpose processor is not enough, try two, four, 16, or more.
Another way to improve hardware performance is to combine something new – multiple cores – with something old – Reduced Instruction Set Computing (RISC) technology. With RISC, less is more based on the uniform register file load/store architecture and simple addressing modes. ARM, for example, has made some enhancements to the basic RISC architecture to achieve a better balance of high performance, small code size, low power consumption, and small silicon area, with the last two factors being important to increasing the core count.
Hardware acceleration necessary, but …
General-purpose processors, regardless of the number of cores, are simply too slow for functions that must operate deep inside everypacket, such as packet classification, cryptographicsecurity, and trafficmanagement, which is needed for intelligent QoS. Because these functions must often be performed in serial fashion, there is limited opportunity to process them simultaneously in multiple cores. For these reasons, such functions have long been performed in hardware, and it is increasingly common to have these hardware accelerators integrated with multicore processors in specialized SoC communications processors.
The number of function-specific acceleration engines available also continues to grow, and more engines (along with more cores) can now be placed on a single SoC. Examples of acceleration engines include packet classification,deep packet inspection,encryption/decryption,digital signal processing, transcoding, and traffic management. It is even possible now to integrate a system vendor’s unique intellectual property into a custom acceleration engine within an SoC. Taken together, these advances make it possible to replace multiple SoCs with a single SoC in many networking systems (see Figure 1).
Figure 1:SoC communications processors combine multiple general-purpose processor cores with multiple task-specific acceleration engines to deliver higher performance with a lowercomponentcount and lower power consumption.
In addition to delivering higher throughput, SoCs reduce the cost of equipment, resulting in a significant price/performance improvement. Furthermore, the ability to tightly couple multiple acceleration engines makes it easier to satisfy end-to-end QoS and service-level agreement requirements. The SoC also offers a distinct advantage when it comes to power consumption, which is an increasingly important consideration in network infrastructures, by providing the ability to replace multiple discretecomponentsin a single energy-efficient IC.
The powerful capabilities of today’s SoCs make it possible to offload packet processing entirely to system line cards such as a router or switch. In distributed architectures like the IP Multimedia System and SDN, the offload can similarly be distributed among multiple systems, including servers.
Although hardware acceleration is necessary, the way it is implemented in some SoCs today may no longer be sufficient in applications requiring deterministic performance. The problem is caused by the workflow within the SoC itself when packets must pass through several hardware accelerators, which is increasingly the case for systems tasked with inspecting, transforming, securing, and otherwise manipulating traffic.
If traffic must be handled by a general-purpose processor each time it passes through a different acceleration engine, latency can increase dramatically, and deterministic performance cannot be guaranteed under all circumstances. This problem will get worse as data rates increase in Ethernet networks from 1 Gbps to 10 Gbps, and in mobile networks from 300 Mbps in 3G networks to 5 Gbps in 4G networks.
Next-generation multicore SoCs
LSI addresses the data path problem in its Axxia SoCs with Virtual Pipeline technology. The Virtual Pipeline creates a message-passing control path that enables system designers to dynamically specify different packet-processing flows that require different combinations of multiple acceleration engines. Each traffic flow is then processed directly through any engine in any desired sequence without intervention from a general-purpose processor (see Figure 2). This design natively supports connecting different heterogeneous cores together, enabling more flexibility and better power optimization.
Figure 2:To maximize performance, next-generation SoC communications processors process packets directly and sequentially in multiple acceleration engines without intermediate intervention from the CPU cores.
In addition to faster, more efficient packet processing, next-generation SoCs also include more general-purpose processor cores (to 32, 64, and beyond), highly scalable and lower-latency interconnects, nonblocking switching, and a wider choice of standard interfaces (SerialRapidIO, PCI Express, USB, I2C, and SATA) and higher-speed Ethernet interfaces (1G, 2.5G, 10G, and40G+). To easily integrate these increasingly sophisticated capabilities into a system’s design, software development kits are enhanced with tools that simplify development, testing, debugging, and optimization tasks.
Next-generation SoC ICs accelerate time to market for new products while lowering both manufacturing costs and power consumption. With deterministic performance for data rates in excess of 40 Gbps, embedded hardware is once again poised to accommodate any additional capabilities required by the data deluge for another three to four years.
